1. Technical Field
The present invention relates to a method of manufacturing semiconductor devices, and more particularly to a method of manufacturing semiconductor devices utilizing silicide technology.
2. Brief Description of the Prior Art
SALICIDE (self aligned silicide) technology is an art where in a metal silicide film is formed on a diffused layer and a gate electrode to decrease the sheet resistance thereof. A method of forming a silicide layer on a diffused layer is disclosed for example, in Japanese Patent Publication TOKKAI-SHO 63-84064. A prior art method of semiconductor manufacture utilizing SALICIDE technology will be described with reference to FIG. 1.
As shown in the drawing, a field insulating film 102, such as silicon oxide (SiO.sub.2), is selectively formed on portions of a P-type silicon substrate 101, for isolation between various elements. Then, a gate insulating film 103, such as a thermally grown SiO.sub.2 film is formed on the surface of an active region between the field insulating portions 102. Next, a polycrystalline silicon film 104 is formed on the surface of the gate insulating film by a CVD (chemical vapor deposition) process, after which inpurities such as phosphorous (P) are doped into the poly crystalline film to decrease the resistance thereof. The polycrystalline film is then etched in a desired pattern to form the gate electrode 104, atop the insulating film 103. Conventionally, N-type impurities, phosphorous for example, are then implanted at low concentration into the silicon substrate 101, with the gate electrode 104 acting as a mask, after which a further SiO.sub.2 film 109 is deposited over the gate electrode 104 and the gate insulating film 103. This SiO.sub.2 film is subjected to anisotropic etching vertically and horizontally relative to the substrate 101 by a reactive ion etching (RIE) process to form side wall spacers 105 on the sides of the gate electrode 104. Then, N-type impurities such as arsenic (As) are implanted at high concentration into the silicon substrate 101 with the side wall spacers 105 acting as a mask, with annealing being then performed to electrically activate the implanted impurities.
The above step forms the N+ type source region 106 and the drain region 107 which are self-aligned relative the gate electrode 104. A N-channel MOS FET is thus formed consisting of the gate electrode 104, the source region 106 and the drain region 107. In such a construction both the source and drain regions will form lightly doped N- regions 106a and 107a at positions under the side wall spacer 105. Hence the above described N-channel MOS FET has a so-called LDD (Lightly Doped Drain) structure wherein the lightly doped region 107a moderates the electric field near to drain region 107. After this a titanium film 108 is formed over the entire surface the above-mentioned elements via a sputtering process.
An annealing process is then performed at 600.degree. C. in an atmosphere of argon (Ar) to react the Ti film 108 where it contacts the gate electrode 104, the source region 106 and the drain region 107. This process converts surface portions of the gate electrode 104, the source region 106 and the drain region 107 into a silicide layer. As shown in FIG. 1, titanium silicide (TiSi) films 109a, 109b and 109c are formed on the surfaces of the gate electrode 104, the source region 106 and the drain region 107, respectively. Finally, the unreacted Ti film is removed using a wet etching process.
In MOS LSIs manufactured according to the above method, the TiSi films 109a, 109b and 109c can decrease the sheet resistances of the gate electrode 104, the source region 106 and the drain region 107.
However, the conventional silicide forming technique described above has a disadvantage in that silicon atoms may `ooze into` the side wall spacer 105 through the silicon substrate 101, so that an undesired TiSi film 109d, shown as a broken line in FIG. 1, is formed on the side wall spacer 105, which is not removable by post etching. This results in an electrical short circuit between the gate electrode 104 and the drain region 107, this phenomenon reduces production efficiency and is responsible for a high number of defective LSIs.